The present invention generally relates to broadband networks. More specifically, the invention is related to a single channel direct memory access block which provides digital subscriber line support for a computer using a PCI bus.
With the advancement of broadband technology, digital subscriber line (DSL) technology provides high-speed communication access over the existing copper telephone line infrastructure, and relieves congestion thereon. DSL does this by taking advantage of an unused frequency spectrum available on standard telephone lines that can be used to carry information. While DSL technology creates channels for communicating data over the telephone lines, plain old telephone service (POTS) frequencies remain free to handle voice traffic. Therefore, only a single line is needed to transmit and receive both voice and data communication traffic.
A DSL modem provides connectivity to a computer by allowing simultaneous transmission and reception of voice and data on a single line. When the DSL modem interfaces with a PCI bus within the computer, a problem occurs because the PCI bus only allows data to be read or written at one time, and not simultaneously. Therefore, while DSL advantageously allows the simultaneous communication of voice and data, the PCI bus cannot support this simultaneous functionality.
Briefly described, the invention is a system and method for supporting DSL communication in a computer having a PCI bus. The invention allows a DSL modem to simultaneously transmit and receive data to a computer. This is performed by using a DSL enabling device, which provides both data flow control and general DSL modem control.
The DSL enabling device comprises a PCI DMA arbitrator, which determines the status of a temporary memory module in response to either a transmit request from a transmit control unit or a receive request from a receive control unit, thereby arbitrating between the transmit control unit and the receive control unit in order to access the temporary memory module. A read/write register specifies priority between the transmit control unit and the receive control unit, and specifies computer memory address locations in which to write, and also sets memory cell length.
A transmit random access memory (RAM) is used to temporarily store data communicated from the computer to the DSL modem until such time as the DSL modem instructs the transmit control unit that it is ready to receive the data. A receive RAM is used to temporarily store data destined for the computer from the DSL modem until such time that the PCI DMA arbitrator instructs the receive control unit that the temporary memory module is ready to receive such data.
The invention has numerous advantages, a few of which are delineated hereafter as examples. Note that the embodiments of the invention, which are described herein, possess one or more, but not necessarily all, of the advantages set out hereafter.
One advantage of the invention is that it provides for simultaneous communication of data between a DSL modem and a computer having a PCI bus, without incurring loss of data.
Another advantage is that it provides an efficient circuit design, having minimal cost, for using a single channel DMA to simultaneously and bi-directionally communicate between a DSL modem and a computer.
Other objects, features and advantages of the present invention will become apparent to one of reasonable skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional objects, features and advantages be included herein within the scope of the present invention, as defined by the claims.